The present invention relates generally to data processing and communication systems, and, more specifically, to a system and method for removing glitches from a bit stream of serially transmitted data.
Electrical circuits generally operate in noisy environments. There are numerous sources that may introduce noise in input or output signals of electrical circuits, for example, reflection due to impedance mismatch between a source and load circuit, inductive and capacitive coupling in the circuit, cross-talk between signal lines, ringing, inter symbol interference (ISI) and other sources of disturbances. Such sources may generate unwanted components in the input or output signals of a transmitter or receiver circuit.
In serial communication systems, a data signal is transmitted serially through a transmission channel and noise from different sources adds glitches to the data signal. The serially transmitted data signal is received at the receiver and includes serially arranged data bits. Each data bit sent through the transmission channel is represented by a high or low voltage level for a predetermined time period or ‘bit duration’, resulting in logic values 1 and 0, respectively. Due to noise and other unwanted components as mentioned above, the logic low signal may overshoot during a bit transition for a short duration and produce a positive glitch. Similarly, the logic high signal may undershoot during a bit transition for a short duration and produce a negative glitch. Due to the overshoots and undershoots, the glitches occur near the bit transitions. However, glitches can occur anywhere in the bit duration due to other sources of disturbances, as mentioned above. For example, glitches can occur at the start, end or in the middle of the received bit stream.
Glitches may result in the wrong determination of the transmitted data bits that are received at the receiver. That is, a logic high signal sent by the transmitter may be determined as logic low and a logic low signal sent by the transmitter may be determined as logic high by the receiver. Thus, the glitches result in a high bit error rate (BER), and degrade the performance of the electrical circuit. Thus, if the glitches in the data signal are not removed, the overall function of the circuit is hampered and erroneous output may be produced.
Existing glitch removal circuits have several drawbacks. For one, they use delay-circuits to remove glitches from a bit stream. Drawbacks in such delay-circuit based glitch removal circuits will be explained in conjunction with FIGS. 1 and 2.
Referring now to FIG. 1A, a circuit diagram illustrating a conventional glitch removal circuit 100 is shown. The glitch removal circuit 100 includes a first combinational delay circuit 104a, a second combinational delay circuit 104b, and first and second NAND gates 108a and 108b. The first and second NAND gates 108a and 108b are connected in series. An input bit stream 102 is provided to a first input of the first NAND gate 108a. The input bit stream 102 is also provided to the first combinational delay circuit 104a and an output 106 of the first combinational delay circuit 104a is provided to a second input of the first NAND gate 108a. An output 110 of the first NAND gate 108a is provided to a first input of the second NAND gate 108b and to the second combinational delay circuit 104b. An output 112 of the second combinational delay circuit 104b is provided to a second input of the second NAND gate 108b. 
FIGS. 1B and 1C illustrate first and second timing diagrams of various signals of the conventional glitch removal circuit 100. FIG. 1B shows the input bit stream 102; intermediate signals 106, 110, and 112; and an output signal 114. In this example, the input bit stream 102 includes a transition from a logic 1 to a logic 0 that has a positive or high glitch ‘G’ in the middle of the input bit stream 102. The first combinational delay circuit 104a introduces a delay ‘d1’ in the input bit stream 102 to generate the intermediate signal 106. The first NAND gate 108a performs a NAND operation on the input bit stream 102 and the intermediate signal 106 to generate the intermediate signal 110. The second combinational delay circuit 104b introduces a delay ‘d2’ in the intermediate signal 110 and generates the intermediate signal 112. The total delay introduced by the first and second combinational delay circuits 104a and 104b in the input bit stream 102 is ‘d2−d1’. Finally, the second NAND gate 108b performs a NAND operation on the intermediate signals 110 and 112 to generate the output signal 114. In this case, to remove the glitch from the input bit stream 102, delay ‘d1’ introduced by the first combinational delay circuit 104a needs to be greater than the duration of the glitch ‘G’, i.e., d1>G. Additionally, the delay ‘d2’ introduced by the second combinational delay circuit 104b needs to be greater than the sum of the delay d1 and the duration of the glitch ‘G’, i.e., d2>d1+G. Thus, the combinational delay circuits 104a and 104b have to be designed specifically to meet the above-mentioned requirements.
The glitch is removed from the input bit stream 102 after performing the steps above and the output signal 114 is a glitch-free bit stream. However, the bit width L of the input bit stream 102 has been shortened to bit width L′, that is the bit width has been shortened by a width equal to ‘d2−d1’. Similarly, if there is a negative or low glitch in the middle of the input bit stream 102 then the bit width L′ is elongated by a width equal to ‘d2−d1’ (see FIG. 1C). This is undesirable because bit width alterations may lead to a high BER at the receiver.
FIG. 1D is another example of a negative glitch in the input bit stream 102. In FIG. 1C, the glitch occurred near the middle of the input bit stream 102 while in FIG. 1D, the glitch occurs closer to a bit transition of the input bit stream 102. Referring to FIG. 1D, the input bit stream 102 includes a transition from a logic 0 to a logic 1 that has a negative or low glitch ‘G’ near the beginning of the transition end in the input bit stream 102. The first combinational delay circuit 104a introduces a delay ‘d1’ in the input bit stream 102 to generate the intermediate signal 106. The first NAND gate 108a performs a NAND operation on the input bit stream 102 and the intermediate signal 106 to generate the intermediate signal 110. The second combinational delay circuit 104b introduces a delay ‘d2’ in the intermediate signal 110 and generates the intermediate signal 112. Finally, the second NAND gate 108b performs a NAND operation on the intermediate signals 110 and 112 to generate the output signal 114. As shown in FIG. 1D, a glitch G′ occurs near the transition end in the output signal 114. The glitch in the input signal occurs at a distance X from the transition end, where the value of X is less than the total delay introduced by the first and second combinational delay circuits 104a and 104b (i.e. X<d1+d2). Thus, the glitch G has not been removed from the input bit stream 102 after performing the steps above and the output signal 114 includes the glitch G′.
It is evident from FIG. 1D, that the conventional glitch removal circuit 100 cannot remove glitches that are present near the transition ends of the signal received at the receiver. Further, it is evident from FIGS. 1B and 1C that the conventional glitch removal circuit 100 alters the bit width while removing glitches present near the middle of the signal received at the receiver. Additionally, in order to remove glitches from the input bit stream there are specific design requirements in the conventional glitch removal circuits.
Referring now to FIG. 2A, a block diagram illustrating another conventional glitch removal circuit 200 is shown. FIG. 2A includes three sequential delay circuits 204a, 204b, and 204c; an XOR gate 210; and a multiplexer 214 (hereinafter “mux 214”). Additionally, a single clock input (not shown in FIG. 2A) is connected to the three sequential delay circuits 204a, 204b, and 204c. The three sequential delay circuits 204a, 204b, and 204c; the XOR gate 210; and the mux 214 are connected in series. An input bit stream 202 is provided to an input of the first sequential delay circuit 204a and an output 206 of the first sequential delay circuit 204a is provided to the second sequential delay circuit 204b. The output 206 is also provided to a first input of the XOR gate 210 and to a first input of the mux 214. Further, an output 208 of the second sequential delay circuit 204b is provided to a second input of the XOR gate 210 and an output 212 of the XOR gate 210 is provided to a second input of the mux 214. The second input to the mux 214 is a control signal that is provided to a select line of the mux 214. An output 216 of the mux 214 is provided to the third sequential delay circuit 204c. Lastly, an output 218 of the third sequential delay circuit 204c is provided to a second input of the mux 214.
FIG. 2B is a timing diagram illustrating various signals in the conventional glitch removal circuit 200. FIG. 2B shows the input bit stream 202; intermediate signals 206, 208, and 212; and an output signal 218. The first sequential delay circuit 204a receives the input bit stream 202, which is generated by oversampling an input bit stream using an oversampling unit (not shown). The input bit stream 202 represents the bit stream that includes a transition from a bit 0 to a bit 1, and there is a negative glitch G near the transition end in the input bit stream 202. The first and second sequential delay circuits 204a and 204b generate the intermediate signals 206 and 208, respectively.
If the intermediate signals 206 and 208 have the same logic values, then the intermediate control signal 212 is logic low, and the intermediate signal 206 is provided as the output of the mux 214 to generate the intermediate signal 216. However, if the intermediate signals 206 and 208 have different logic values, then the intermediate control signal 212 is logic high, and the current output signal 218 is provided as the output 216 of the mux 214.
The third unit delay circuit 204c introduces a unit delay in the intermediate signal 216 to generate the output signal 218, which is fed back to the mux 214. The mux 214 holds the output at the previous logic value of the input bit stream 202 during bit transitions in the input bit stream 202 and updates the output when there is no bit transition in the input bit stream 202. The sequential delay circuits 204a, 204b, and 204c store previous and present values of the input bit stream 202 to be used by the mux 214. Thus, the glitch in the input bit stream 202 is removed by maintaining the previous logic value, i.e. high or low at the output signal 218 during the bit transitions in the input bit stream 202 and updating the new logic value at the output signal 218 during the bit non-transitions in the input bit stream 202. However, a major shortcoming of the conventional glitch removal circuit 200 is that the bit width L in the input bit stream 202 is shortened to bit width L′ in the output signal 216.
Data processing and communication systems based on serial data transmission are particularly sensitive to glitches. High-Speed serial interfaces, such as Mobile Industry Processor Interface (MIPI), Serial AT Attachment (SATA), Universal Serial Bus (USB) 3.0, and Peripheral Component Interconnect (PCI) Express, use various clock and data recovery schemes. These clock and data recovery schemes rely on accurate detection of bit boundaries. Therefore, the clock and data recovery schemes are particularly sensitive to glitches. Additionally, for error free clock and data recovery and to maintain low BER at the receiver of the High-Speed serial interfaces, the input bit stream provided to the clock and data recovery circuit should include bits of equal widths (i.e., no shortening or elongation of bit widths) corresponding to logic low and logic high data.
The conventional glitch removal circuits undesirably alter the bit widths while removing glitches from the received bit stream. Consequently, the probability of recovering correct data at the receiver by the clock and data recovery circuit decreases. It is desirable that the glitch removal circuits remove glitches of variable width and glitches that occur anywhere during the bit duration. Further, the delay introduced by the delay elements in the conventional glitch removal circuits varies with process, voltage, and temperature (PVT) variations, and hence, glitch removal operation is sensitive to the operating range of the circuit. It would be advantageous to have a glitch removal circuit that is independent of PVT variations. It also would be desirable to have a glitch removal circuit that can remove variable width glitches and does not alter the bit width of the input bit stream.